Starship2
Member
yep, alright. got it now.Maybe you're misunderstanding my post, "four 64MiB 16-bit" mean four 16-bit chips total on the board. Each channel of cell have two chip connected to. Cell have two channel 32-bit each, this means 64-bit total, 64 DQ/DQN pins. Perfectly fit all the chips.
Bits is all about bandwidth, 64-bit total is maximum that cell can do. You can use bigger chips, more bits but there is no more DQ pin on cell to be connected to so it must left float. Then configure each chip to run at lower bandwidth/bits. You will get more capacity but total bandwidth still same.
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that would be an alternative if its possible to pick other chips with higher bandwith by just reducing bandwith. didnt know thats possible. im not that familiar with ram, didnt mess around with it a lot in the past so i do have to learn many things about it. aint got no idea how addressing ram actually works, im just looking at it from a sheer mechanical perspective.